In the manufacture of a semiconductor device, several contacting process are required. For example, in the semiconductor device in which a first conducting line, a first interlayer insulating layer, a second conducting line, a second interlayer insulating layer and a third conducting line are formed sequentially, it is often the case that said third conducting line is connected to the first conducting line after passing through the second conducting line. In this case, in order to insulate the first and third conducting lines from the second conducting line, contact areas for the third conducting line and the first conducting line must maintain a certain distance from the second conducting line. Accordingly, contact masks for the third conducting line and the second conducting line must follow a certain design rule during the manufacturing process. That is, in the design of the third conducting line contact mask that is used to contact the third conducting line to the first conducting line, the contact for the third conducting line must maintain a certain distance from the second conducting line. Therefore, since the registration, critical dimension variation, misalignment tolerance and lens distortion generated during the masking process, as well as the thickness of insulation layer between the third conducting layer contact and the second conducting layer must be considered carefully, the size of the contact increases. Accordingly, the problem of increased space caused by the requirement to maintain a certain distance between the third conducting line contact mask and the second conducting line mask is solved by a self-aligned contact forming method. As a result, the space occupied by the contact is reduced as the distance between the third conducting line contact mask and the second conducting line mask are decreased. However, if the conventional self-aligned contact forming method is used, a vertical topological difference becomes so great that etching away the conducting material for the third conducting line becomes a difficult process. Also, the other conventional method that tries to solve this problem restricts the amount of space to be reduced.
FIG. 1 is a plane view of the semiconductor device during the forming of the self-aligned contact. For the sake of convenience, only a charge storage electrode contact C, bit line B, and source/drain electrode A are illustrated.
FIG. 2A through FIG. 2D are cross sectional views shown along I--I of FIG. 1 that illustrate the manufacturing steps of the semiconductor device using a conventional self-aligned method. As shown in FIG. 2A, a field oxide layer 2 is formed on certain part of the semiconductor substrate 1 and a source/drain electrode 3 on the active area. After that, a first interlayer insulating layer 4, conducting material 5 for bit lines, and a second interlayer insulating layer 6 are formed sequentially.
Next, as shown in FIG. 2B, said second interlayer insulating layer 6, conducting material 5 for bit lines, and the first interlayer insulating layer 4 are etched sequentially using a bit line mask to form a bit line 5'. Then, an insulating layer 7 for side wall spacer is formed on the side wall of said bit line 5' for insulation purpose. Then, a photoresist layer is coated to form a charge storage electrode contact mask 8. FIG. 2B shows that the charge storage electrode contact mask 8 is misaligned as much as the distance created while the masking process. Therefore, said charge storage electrode contact mask 8 does not cover the bit line 5' completely.
As shown in FIG. 2C, the insulating layer 7 for a spacer is etched to a certain thickness using the charge storage electrode contact mask 8 to expose the source/drain electrode 3 so that insulation layers 6 and 7' is left on top and side wall of the bit line 5' for insulation purpose. And then, a conducting material 9 for a charge storage electrode is formed over the entire structure and a charge storage electrode mask 10 is formed. The figure shows a drastic topological difference caused by the above-said first interlayer insulating layer 4, bit line 5', and the second interlayer insulating layer 6. Also, it indicates the part 40 where the most drastic topological difference may take place during etching the conducting material 9 for the charge storage electrode.
FIG. 2D is a cross sectional view illustrating the forming of a charge storage electrode 9' by etching the conducting material for the charging storage electrode using the charge storage electrode mask 10. As shown in the figure, residual 49 of the conducting material is left on the part experiencing a great topological difference caused by said first interlayer insulating layer 4, the bit line 5', and the second interlayer insulating layer 6. The residual 49 may the other conducting lines during the later processes, causing defects in semiconductor device.
As described so far, when the conventional method of forming the self-aligned contact is used, occurrence of a great topological difference becomes a serious problem.
FIG. 3A through FIG. 3C are cross sectional views shown along I--I of FIG. 1 that illustrate the manufacturing steps of the semiconductor device in accordance with another conventional method. This method has decreased the topological difference so that the conducting material for the charge storage electrode can be etched more easily.
Referring to FIG. 3A, a field oxide layer 2 is formed on a certain part of the substrate 1 of the semiconductor device. Then, a first interlayer insulating layer 4 and a bit line 5' are formed after forming a source/drain electrode 3. Next, a second interlayer insulating layer 16 is formed and flattened. Then, a photoresist layer is coated to form a contact mask 8 for the charge storage electrode. FIG. 3A shows that said charge storage electrode contact mask 8 is misaligned and does not cover the bit line 5' completely.
FIG. 3B is a cross sectional view that illustrates the following: the source/drain electrode 3 is exposed by etching the second interlayer insulating layer 16 and the first interlayer insulating layer 4 using said charge storage electrode contact mask 8; then, an insulating layer 17 for spacers is formed on the entire side wall of the bit line 5'.
As shown in the figure, the bit line 5' is misaligned as much as the distance created during the masking process so that some of the upper part and side wall of the bit line 5' is exposed as much as the part not being covered with said charge storage electrode contact mask 8 when the insulating layers 16 and 4 are etched. If the insulating layer 17 for said spacers is thicker than the exposed part of the upper part of said bit line 5', the contact area to be formed on the source/drain electrode 3 is decreased, making the contact with the charge storage electrode difficult. If said insulating layer 17 is less thick than the exposed part, a side wall 50 on the upper part of said insulating layer 17 for spacers will be located on the same vertical plane as the side wall of the exposed bit line 5' will be.
FIG. 3C is a cross sectional view illustrating the forming of the insulating layer spacer 17' on the side wall of said bit line 5' by etching back said insulating layer 17 for spacers. It should be noted that said insulating layer 17 for spacers is less thick than the exposed part of the upper part of said bit line 5', the exposed side wall of said bit line 5' is insulated by the said insulating spacer 17'. However, its top part 50' is not insulated by the insulating spacer 17', causing a short between the charge storage electrode and the bit line in later processes. The prevent this from occurring, the interval between the bit lines of the charge storage electrode contact mask should be reduced to a certain point and no more. If the above described another conventional method is applied, the conducting material for a charge storage electrode can be easily etched due to an improvement in the topological difference. However, it restricts the contact area to be reduced.